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ZL20200
Dual Band IS136/AMPS Transceiver Data Sheet
Features
* * * * * * * * * * Dual Band IS136 (800/1900 MHz) Compatible Fully Integrated Dual Band Transceiver Receive - IF to Baseband I and Q Transmit - Baseband I / Q to RF Integrated Filters FM Demodulator RF and IF Synthesizers Fully Programmable via serial bus 3 Volt operation Small scale package
Ordering Information ZL20200/LDG ZL20200/LDF ZL20200/LDG1 ZL20200/LDF1 56 Pin QFN Trays, 56 Pin QFN Trays, 56 Pin QFN* Trays, 56 Pin QFN* Trays, *Pb Free Matte Tin -40 to +85C Bake Bake Bake Bake & & & & Drypack Drypack Drypack Drypack
November 2006
Description
The ZL20200 is a fully integrated transceiver for dual band IS136/AMPS handsets. The IF input to the receive path is amplified and down-converted to baseband I and Q signals. Gain control is provided. Baseband filtering is also included. A FM demodulator is also provided to support AMPS operation. The transmit path consists of a quadrature modulator, gain control at IF and up-conversion to RF. Dual band RF outputs are provided. The transmit output stages can be programmed to optimize performance and current consumption.
Applications
* * * * Dual Band (850/PCS1900) TDMA/AMPS Mobile Telephones Cellular 850 MHz TDMA/AMPS Mobile Telephones PCS1900 TDMA Mobile Telephones Cellular Telematic Systems
Rx I IS136 90 Rx Q FM Demod Rx VHF PLL Tx VHF PLL UHF PLL
Serial Interface Control
FM RSSI LOCK DET
UHF LO O/P UHF VCO
900 MHz Tx IQ Mod 1900 MHz Tx
Tx I Tx Q
Tx IF Filter (Opt)
Figure 1 - Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL20200
Data Sheet
ZL20200 also includes a fractional N RF synthesizer and two IF synthesizers to provide all local oscillator signals required. Flexible programming is provided via a 3 wire serial bus. Additional control pins allow accurate timing control when switching between modes.
Package Diagram
VCC CO NTROL
VCC RX PLL
RX VCO +
RX VCO -
RX GAIN
VCC RX
IF1 IN+
IF1 IN-
FM O UT
FM FB
RX I+
RX I-
NC
NC
SDAT SCLK SLATCH TCXO VCC UHF PLL UHF CP VCC UHF LO OUT 900 LO OUT 1900 LO OUT RESETB ENABLE1 900 LO IN VCC UHF LO 1900 LO IN TX FILT O UT+ TX FILT O UTTX DEG1900 TX FILT IN+ TX DEG900 VCC TX RF TX FILT INENABLE2 TX G AIN TX 1900 VCC TX TX 900 TX Q + TX Q -
RX QRX Q+ RSSI RX CP VCC VHF CP ISET
ZL20200
LOCK DET TX CP TX RXB TX ITX I+ VCC TX PLL TX VCOTX VCO+
Figure 2 - ZL20200 Package Diagram
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Zarlink Semiconductor Inc.
ZL20200
Pin Description
Pin Description Table No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Pin Name SDAT SCLK SLATCH TCXO VCC UHF PLL UHF CP 900 LO OUT 1900 LO OUT RESETB ENABLE1 900 LO IN VCC UHF LO 1900 LO IN VCC TX RF TX 900 TX DEG900 TX DEG1900 TX 1900 ENABLE2 TX GAIN TX FILT IN+ TX FILT INVCC TX TX FILT OUT+ TX FILT OUTTX Q+ TX QTX VCO+ TX VCOVCC TX PLL TX I+ TX ITX RXB TX CP LOCK DET ISET Power Input Input Input Output Output Output Input Input Input Input Power Output Output Input Input Type Input Input Input Input Power Output Output Output Input Input Input Power Input Power Output Serial Interface - Data Serial interface - Clock Serial Interface - Latch Reference input from TCXO Power UHF PLL Charge Pump Output Power to LO output stages 900 MHz buffered LO output to external receiver mixer Description
Data Sheet
VCC UHF LO OUT Power
1900 MHz buffered LO output to external receiver mixer Reset (Active low) Mode Control 900 MHz LO input Power to UHF LO input stage 1900 MHz LO input Power to transmit RF output stages 900 MHz transmit output Degeneration for 900 MHz output - Connect to Ground Degeneration for 1900 MHz output - Connect to Ground 1900 MHz transmit output Mode Control Transmit gain control Input from transmit IF filter (optional) Power to transmit stages Output to transmit IF filter (optional) Q transmit signal from baseband Transmit Oscillator tank circuit Power to Transmit VHF PLL I transmit signal from baseband Transmit / Receive control Transmit VHF PLL charge pump output PLL Lock Detect Output Connect 50 kohm resistor to ground to set internal reference current
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Zarlink Semiconductor Inc.
ZL20200
Pin Description Table (continued) No 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Pin Name VCC VHF CP RX CP RSSI RX Q+ RX QRX I+ RX IFM OUT FM FB RX VCORX VCO+ VCC RX PLL VCC RX RX GAIN NC NC IF1 INIF1 IN+ VCC CONTROL Input Input Power Power Power Input Type Power Output Output Output Output Output Output Output Description Power to VHF charge pump outputs Receive VHF PLL charge pump output RSSI Output Baseband Q signal Baseband I signal Demodulated FM output Feedback to FM output stage Receive second LO Oscillator tank circuit Power to receive VHF PLL Power to receive stages Receive gain control Not Connected Not Connected IF Input (1) IS136 Input Power to serial interface logic
Data Sheet
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Zarlink Semiconductor Inc.
ZL20200 Table of Contents
Data Sheet
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.1 IS136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.2 AMPS FM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 UHF LO and Frequency Doubler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 UHF Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 VHF Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.6 Internal Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.7 VHF VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.8 Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.0 Programming and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 Power Control Registers - Address 0 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.1 Power Control Modes - TDMA (IS136) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1.2 Power Control Modes - AMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2 Operating Register Address 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 Synthesizer Register - Address 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 UHF PLL and LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.2 UHF PLL Charge Pump Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.3 Receive LO Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.4 Transmit LO Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 Control Register - Address 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.1 IS136 Baseband Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.2 TCXO Reference Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.3 Discriminator Output Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.4 Transmit Baseband Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.5 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5 Register Address 7 - Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 Test Mode Register - Address 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.7 UHF PLL Divider Programming Register - Address 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8 UHF PLL Reference Divider and Fractional N Programming Register - Address 10 . . . . . . . . . . . . . . . . 36 2.9 Receive VHF PLL Divider Programming Register - Address 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.10 Receive VHF PLL Reference Divider Programming Register - Address 12 . . . . . . . . . . . . . . . . . . . . . . 37 2.11 Transmit VHF PLL Divider Programming Register - Address 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.12 Transmit VHF PLL Reference Divider Programming Register Address 14 . . . . . . . . . . . . . . . . . . . . . . . 37 2.13 PLL Lock Detect & Fractional N Compensation Programming Register Address 15 . . . . . . . . . . . . . . . 37 2.13.1 Fractional N Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.13.2 PLL Lock detect counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.0 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.0 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Zarlink Semiconductor Inc.
ZL20200 List of Figures
Data Sheet
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL20200 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3 - ZL20200 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - IS136 Receiver Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - AMPS Receive Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7 - External Transmit IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - UHF Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9 - Count Sequence for UHF PLL with 4 Modulus Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10 - UHF Synthesizer - Fractional N Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11 - VHF Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12 - Typical VCO Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13 - Serial Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14 - Transmit Output Stage Current versus Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Zarlink Semiconductor Inc.
ZL20200 List of Tables
Data Sheet
Table 1 - IS136 Receive Gain and Filter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2 - AMPS FM Receive Gain and Filter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3 - Transmit Circuit blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5 - Power Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6 - Power Control Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7 - Programming for the Power Control Registers (0 - 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8 - Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9 - Function of the Receive Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10 - Function of the Transmit Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11 - Gain of the Transmit Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12 - VGA Threshold Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13 - VGA Current Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14 - Output Stage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15 - Control Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16 - UHF PLL and LO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 17 - Fractional N Denominator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18 - UHF PLL Charge Pump Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19 - Receive LO Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20 - Receive VHF PLL Charge Pump Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 21 - Transmit LO Set Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22 - Transmit VHF PLL Charge Pump Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 23 - Baseband Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 24 - TCXO Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 25 - FM Discriminator Output Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 26 - Transmit Baseband Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 27 - Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Zarlink Semiconductor Inc.
ZL20200
1.0 General Description
Data Sheet
A detailed block diagram is shown in Figure 3. This shows the receive and transmit paths plus the LO generation circuitry. Control is via a serial bus with the addition of direct inputs to control receive and transmit modes and optimize power consumption.
43 RX I+ 44 RX I-
IF1 IN+ 55 IF1 IN- 54
/2
RX GAIN 51
AMPS demod. and RSSI
60kHz
45 FM OUT 46 FM FB 40 RSSI 41 RX Q+ 42 RX Q-
/N /2
S y n th P r o g r a m m i n g
PLL
RX VCO- RX VCO+ VCC RX 50 47 Tank Circuit 48 Loop Filter 39 RX CP
OUT
VCC UHF LO
VCC UHF LO
Control
I SET 37 VCC RX PLL 49
TCXO 4
36 LOCK DET
13
7 900 LO IN 12 Loop Filter Option 14 1900 LO IN UHF CP VCC UHF PLL VCC TX PLL 31 VCC VHF CP 38 Loop Filter TX CP
Control
10 11 20 34
RESETB ENABLE1 ENABLE2 TX RXB
TX VCO+
TX VCO-
1900 LO OUT 900 LO OUT
56 VCC CONTROL 1 SDAT 2 SCLK 3 SLATCH
9 8
LO Select and Doubler
Tank Circuit
Serial interface
6
5
30
29
35
PLL PLL
TX 1900 19
/2 /2 MUX
/2
32 TX I+ 33 TX I-
27 TX Q+ 28 TX Q-
TX 900 16
T X F IL T O U T +
T X F IL T O U T -
T X D E G 1900
T X D E G 900
T X F IL T IN -
T X F IL T IN +
VCC TX RF
T X G A IN
18
17
15
23
22
Option
25
26
21
24
Figure 3 - ZL20200 Detailed Block Diagram
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Zarlink Semiconductor Inc.
VCC TX
ZL20200
1.1 Receive Path
Data Sheet
The IF input receives an input signal from IS136/AMPS filter. The differential input stage is followed by an agc amplifier. Gain control is provided from an external analog voltage. After the agc amplifier the signal is then downconverted to a low IF frequency and the signal flow then depends on the mode selected. All internal signals are differential. The LO frequency for the down conversion is derived from an on chip oscillator and PLL. The LO frequency can be programmed to be either oscillator frequency divided by 2 or 4. When in divide by 2 mode a DLL (Delay Locked Loop) circuit can be selected to maintain accurate quadrature. It is particularly important to have good quadrature in IS136/AMPS modes using a low IF frequency, to achieve the required image rejection in conjunction with the following polyphase bandpass filter. It is also possible to programme high side or low LO injection. Each receive mode will now be described in more detail
1.1.1
IS136
The IS136 receive signal path is shown in detail in Figure 4 and performance for each stage is summarized in the following table. Filter Bandwidth (If Applicable)
Circuit Block IF Input (IF1) AGC Amplifier Quadrature Down-converter Anti-alias filter Band Pass Filter
Gain (dB) 26 max
Description Differential IF input stage AGC Amplifier - Gain control range 90 dB Down-conversion to 60 kHz IF
47 230 kHz +/- 20 kHz Low pass Butterworth (n= 3) Switched capacitor polyphase Chebyshev. Also provides typically 30 dB image rejection. Centre frequency = 60 kHz. Clock frequencies 1.44 MHz and 720 kHz.
Gain Stage Baseband Down-converter Baseband filter 1 Baseband filter 2 7 37.5 kHz 60 kHz Down conversion to baseband I and Q signals Switched capacitor low pass Chebyshev. Clock frequency = 240 kHz Smoothing filter. Low pass Butterworth
Table 1 - IS136 Receive Gain and Filter Distribution The output of the agc amplifier is down-converted using a quadrature mixer to a low IF of 60 kHz. High side or low side LO injection can be selected. The In Phase (I) and Quadrature (Q) signals at 60 kHz are then passed through anti alias filter stage to remove any high frequency signals prior to subsequent sampling. The 60 kHz IF signals are then fed into a switched capacitor polyphase bandpass filter which not only provides filtering but also provides image rejection. This switched capacitor filter provides very stable performance and no calibration is required. After the bandpass filter the 60 kHz IF signal is further amplified and then mixed down to baseband I and Q signals. Additional filtering is required at baseband to remove spurii from the down-converter. This filtering is provide in two stages, the first stage is a switched capacitor filter with the second stage being a smoothing filter to remove clock breakthrough from the preceding switched capacitor filter. The differential baseband outputs can then be fed directly into analog to digital converters on a baseband processor.
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Zarlink Semiconductor Inc.
R e c e iv e
B aseband
IF
In p u t
AGC Q u a d ra tu re A m p lifie r D o w n c o n v e r te r A n ti A lia s F ilte r B aseband F ilte r 1 B aseband F ilte r 2
I
IF 1
G a in 60 kH z
Band P ass F ilte r
A n ti A lia s F ilte r
B aseband F ilte r 1
B aseband F ilte r 2
Q
ZL20200
10
Q u a d ra tu re D iv 2 / D iv 4 R e c e iv e VHF VCO R e c ie v e VH F PLL Rx VHF PLL Tank C ir c u it Loop F ilte r
Figure 4 - IS136 Receiver Signal Flow
Zarlink Semiconductor Inc.
L im ite r RSSI RSSI
RSSI
FM D is c r im in a to r
Data Sheet
ZL20200
1.1.2 AMPS FM
Data Sheet
FM demodulation can be performed using the I and Q baseband signals if supported by the baseband. However the ZL20200 also contains an FM demodulator, the AMPS receive signal path using this mode is shown in detail in Figure 5 and performance for each stage is summarized in the following table. Filter Bandwidth (If Applicable)
Differential IF input stage AGC Amplifier - Gain control range 90 dB. Includes IF input stage gain. Down-conversion to 60 kHz IF 230 kHz 73 +/- 16 kHz Low pass Butterworth Switched capacitor polyphase Chebyshev. Also provides typically 30 dB image rejection. Centre frequency = 60 kHz. Clock frequency 1.44 MHz and 720 kHz. Provides limited output to discriminator. Also provides RSSI output. Digital FM discriminator 30 kHz 25 kHz Smoothing filter. Low pass Butterworth. Provides filtering of FM discriminator output. Switched capacitor low pass Chebyshev. Clock frequency = 240 kHz. Provides additional filtering of discriminator output. Selected using PDF and LPC bits Switched capacitor low pass Chebyshev. Clock frequency = 240 kHz. Provides additional filtering of discriminator output. Selected using PDF and LPC bits Smoothing filter. Low pass Butterworth. Provides filtering of FM discriminator output. Configured using external components as bandpass filter.
Circuit Block
IF Input (IF1) AGC Amplifier Quadrature Down-converter Anti-alias filter Band Pass Filter
Gain (dB)
Description
26 max
Limiter FM Discriminator Baseband filter 2 (I Channel) Baseband filter 1 (I Channel) Baseband filter 1 (Q Channel) Baseband filter 2 (Q Channel) FM Output
25 kHz
60 kHz 30 kHz
Table 2 - AMPS FM Receive Gain and Filter Distribution The signal path is initially the same as for IS136 with the down conversion to 60 kHz and channel filtering in the bandpass filter. In FM mode however, the baseband I and Q output stages are disabled, and the 60 kHz IF signal from the bandpass filter is input to a limiting amplifier and FM discriminator. The FM discriminator consists of a shift register acting as a delay line. The output of the discriminator is a digital signal which must then be filtered to recover the audio signal. The discriminator output is therefore routed through the baseband I and Q filters. The default condition is to use the cascaded I and Q smoothing filters (baseband filter 2) with the cut-off frequency set to 30 kHz. This connection is automatically selected when programming FM mode. There is an option to use the cascaded switched capacitor filters (baseband filter 1) with the cut off frequency set to 25 kHz to provide extra filtering. These filters are selected using the PDF and LPC bits in control register 6 and are inserted between the smoothing filters as shown in Figure 5. The final output stage uses external feedback components to provide a bandpass filter with a bandwidth of at least 300 Hz to 10 KHz to cover the demodulated audio and control signals. The feedback components can be modified to change the output level to optimize compatibility with baseband.
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Zarlink Semiconductor Inc.
ZL20200
Data Sheet
A RSSI output is provided. This is a full wave rectified output of the 60 kHz IF and therefore has a high 120 kHz content. This requires an external low pass filter - typically 10 kohm and 2.7 nF. There is a trade-off between settling time and filtering. This is different to conventional RSSI circuits which operate at typically 450 kHz which is much easier to filter. Although the AMPS receive path includes a limiting amplifier, gain control is also required. This is because the band pass filter has limited dynamic range (50 dB). At low signal levels the agc should be set to 1.6 volts to set the gain 20 dB below maximum to obtain optimum signal handling and noise performance. At higher signal levels the gain setting should be reduced to maintain the RSSI level approximately 10 dB below maximum. Gain control would be provided by the baseband controller which would also monitor the RSSi level. Fine gain control is not required and can be implemented in large steps e.g. 20 dB, allowing the use of a relatively slow gain control loop giving optimum performance under fading conditions.
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Zarlink Semiconductor Inc.
R e c e iv e
B aseband
IF
In p u t
AGC Q u a d ra tu re A m p lifie r D o w n c o n v e r te r A n tiA lia s F ilte r B aseband F ilte r 1 B aseband F ilte r 2
I
IF 1
G a in 60 kH z
Band P ass F ilte r
A n ti A lia s F ilte r
B aseband F ilte r 1
B aseband F ilte r 2
Q
ZL20200
13
Q u a d ra tu re D iv 2 /D iv 4 R e c e iv e VHF VCO R e c ie v e VH F PLL Rx VHF PLL RSSI Tank C ir c u it Loop F ilte r
Figure 5 - AMPS Receive Signal Flow
Zarlink Semiconductor Inc.
L im ite r RSSI
RSSI
FM D is c r im in a to r
FM
OUT
FM
FB
Data Sheet
ZL20200
1.2 Transmit
Data Sheet
Transmit operation is similar for all modes and a detailed diagram is shown in Figure 7. This diagram also shows the UHF LO generation circuit blocks. A summary of the characteristics of the transmit path circuit blocks are given in the table below. All circuit blocks are differential with the exception of the transmit RF outputs.
Circuit Block Reconstruction Filters Gain (dB) 0 -12 Bandwidth (If Applicable) IS136/AMPS 12.5 kHz
Description Baseband input stage. Gain is programmable in 3 dB steps from 0 to 12 dB. There is also a by-pass mode so that the baseband I and Q signal can go direct to the modulator Generates a modulated IF signal
Quadrature Modulator Transmit IF 400 MHz
Provides gain control at IF frequency. This stage also includes a low pass filter to remove harmonics and spurii from modulator output. This stage also includes a buffered IF output which can be used with an external IF filter. SSB up-converter to RF frequency. The IF path includes phase shift networks for the up-converter. This stage also includes the input circuit from the optional external IF filter The 900 MHz and 1900 MHz RF stages each consist of 2 stages. The first stage gain be set from -6 to +3 dB in 3 dB steps. Output stage current is controlled by agc signal to reduce current consumption at low output power levels. Each output stage requires an external degeneration inductor
Up-converter
Transmit RF
Table 3 - Transmit Circuit blocks Differential baseband transmit I and Q signals from a baseband processor are input to the ZL20200. The baseband signals are passed through filters. A quadrature modulator modulates these baseband signals on to the transmit IF which is typically around 200 MHz. This modulated IF signal is passed through an on chip low pass filter which removes harmonics of the IF and then into a gain controlled amplifier. This amplifier is controlled by an external analog signal and provides greater than 60 dB gain control The output of the gain controlled amplifier can then be up-converted to RF or alternatively the output can be sent to an off chip filter to provide further filtering and removal of noise before up-conversion. This filter is a parallel tuned circuit as shown in Figure 7. The choice of component values is dependent on the IF frequency being used. The filter output is then fed back on chip to the up-converter. A SSB mixer is used for the up-conversion to remove the unwanted image. High side or low side LO injection can be selected. A buffer amplifier after the up-conversion provides a further 9 dB gain control in 3 dB increments. This gain is programmable via the serial bus and can be used to optimize noise and linearity performance in particular applications. Finally there are two RF output stages for 900 MHz and 1900 MHz frequency bands. Each RF output is single ended and requires a simple matching network. The supply current of the output stages is automatically reduced at low transmit gain control voltages improving the efficiency of the output buffer at low output power levels. The supply current of the output buffer can also be controlled via the serial bus. This allows the supply current to be reduced which is particularly useful when using AMPS where the linearity performance is less critical. The FM modulation for AMPS can be done using I,Q modulation if available. Alternatively FM modulation can be applied direct to the transmit IF VCO. The loop bandwidth for the transmit VHF PLL should be low (~100 Hz) to ensure the PLL does not remove the modulation. A dc voltage should be applied across the Tx I+, Tx I- and the Tx Q+, Tx Q- inputs to switch the modulator and generate an IF carrier signal. With a baseband gain of 0 dB a dc voltage of at least 1.5 volts should be applied; a lower voltage can be used with the baseband gain increased to compensate. It is assumed that this bias can be provided by the baseband however if this is not possible then the simplest solution is to connect 200 kohm resistors between I+, Q+ inputs and Vcc and 200 kohm resistors between I-, Q- inputs and ground, assuming the transmit outputs from the baseband are in a high impedance state in AMPS
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Zarlink Semiconductor Inc.
Optional External Transmit IF Filter
TX FILT IN +/Transmit IF
TX FILT OUT +/-
Transmit RF
Transmitter Upconverter IF Input +/4 Baseband Transmit Filter
Transmit Quadrature Modulator
Transmit Reconstruction Filters
TX 1900
TX I+/-
TX DEG1900
Mux Mux
Low Pass Filter
Optional By-pass Mode
TX 900
-/4
Baseband Transmit Filter
TX Q+/-
ZL20200
15
Quadrature Mux UHF Synthesiser Transmit UHF LO Frequency Doubler Mux Mux UHF PLL UHF LO Input Buffer
TX DEG900
Quadrature
mode. These resistors do produce a small dc offset in TDMA mode when the I and Q inputs are in use, however this is insignificant if the output impedance of baseband transmit outputs is less than 1 kohm. As the FM modulation is applied direct to the VCO in this mode and is external to the ZL20200, any necessary filtering of the FM signal must be provided externally.
Figure 6 - Transmit Path
Zarlink Semiconductor Inc.
Transmit VHF VCO
1900 LO OUT
Div2 / Div4
900 LO OUT
Tx VHF PLL
UHF LO Buffer
Transmit VHF PLL
900 LO IN
900MHz VCO 1900MHz VCO
1900 LO IN
UHF CP
Loop Filter
TX VCO+/Tank Circuit
TX CP
Loop Filter
Data Sheet
ZL20200
Data Sheet
Figure 7 - External Transmit IF Filter
1.3
UHF LO and Frequency Doubler
Figure 7 also shows the UHF LO buffering and frequency doubler. The ZL20200 is designed to operate either with separate external UHF VCOs for the 900 and 1900 MHz frequency bands, or alternatively a single 900 MHz VCO can be used with the on-chip frequency doubler providing the LO for the 1900 MHz band. A UHF synthesizer is included. The input to the UHF synthesizer will normally be the active UHF LO signal, however when using the frequency doubler mode for 1900 MHz LO generation, the synthesizer input can be selected to be either the frequency doubler output or the 900 MHz input LO signal. The UHF LO input buffer minimizes any load pulling effects on the UHF VCO when internal modes are switched. UHF LO output buffers are also provided. These can be used to drive an external mixer for the receive section. If not required these buffers can be powered down.
1.4
UHF Frequency Synthesizer
A fractional N UHF synthesizer is included on the ZL20200 to provide LO signals for the transmit up-converter and the external receive RF down-converters. The UHF synthesizer operates with an external VCO. A block diagram of the synthesizer is shown in Figure 8.
.
Lock Detect TCXO Reference Counter 14 bit Phase Detector UHF LO Quad Modulus Prescaler 64/65/72/73 +1 +8 B 3 bit Fractional N Counter A 4 bit Frac N Compensation 8 bits M Counter 13 bit Charge Pump UHF CP
+1
5 bits Fractional N Compensation DAC
Fractional N Scaling DAC
Figure 8 - UHF Synthesizer
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Zarlink Semiconductor Inc.
ZL20200
Data Sheet
The synthesizer uses a 4 modulus prescaler with an 'M' counter and 'A' and 'B' swallow counters together with a fractional N counter in the UHF counter allowing maximum flexibility. The reference counter is a simple 14 bit counter. All counter values are programmed via the serial bus and programming details are shown in the programming section. Each of the counters operates as count down. At the start of a count the counters are loaded with their respective values. The initial prescaler ratio is dependent on the values loaded into the A and B counters; when both the A and B counters reach zero the prescaler ratio is 64 and then remains until the M counter reaches zero. The complete process is then repeated. This can be shown in a simple example where M = 9, A = 4 and B = 2 which gives a total divide ratio of 596. The count sequence is shown in Figure 9.
M Counter
9
8
7
6
5
4
3
2
1
9
8
A Counter +1 Prescaler B Counter +8 Prescaler
4
3
2
1
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
0
2
1
Prescaler
73
73
65
65
64
64
64
64
64
73
73
Figure 9 - Count Sequence for UHF PLL with 4 Modulus Prescaler At the start of the count sequence the '+1' and '+8' controls to the prescaler are both asserted and the prescaler ratio is 73. After 2 cycles only the '+1' control is asserted and the divide ratio is 65. After a further 2 cycles the A counter reaches zero as well and the prescaler ratio is 64 for the remainder of the count sequence. At the end of the sequence all counters are reloaded and the sequence repeats. The total divide ratio (N) for this type of counter is given by N = 64*M + 8*B + A M is always greater then A or B A value of A = 0 does not support fractional N operation. Valid values of A are 1 to 8. The values of M, B and A can be easily calculated from the total divide ratio as shown below. M = INT ((N - 1)/64) B = INT (((N - 1) - 64*M)/8) A = N - 64*M - 8*B The value of M must always be greater than A or B. The maximum value of B is 7.
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Zarlink Semiconductor Inc.
ZL20200
Data Sheet
The UHF synthesizer also includes a fractional N capability which allows the use of higher comparison frequencies but maintain narrow channel spacing. The use of higher comparison frequencies allows faster loop settling and reduces comparison spur level. This is particularly important in TDMA mode where settling times of < 1.5 ms are required and still obtain good spur performance. Fractional N allows the use of non-integer divide ratios. For example if the total divide ratio is N + 1/5 the counter will divide by N for 4 count cycles and N+1 on the fifth cycle giving the required total divide ratio over five cycles. The ZL20200 can use 5,8,13 or 20 as the fractional denominator (also referred to as the fractional modulus) allowing maximum flexibility in the choice of comparison frequencies. An extra counter - fractional N counter - is required. The input to this counter is from the M counter output. The fractional N modulus can be programmed to be 5,8,13, or 20. Each output pulse from the M counter will increment the fractional N divided by the required fractional numerator. For example if the fraction is 2/5 then the fractional N counter will increment by 2 for each output pulse from the M counter. When the fractional N counter overflows the A counter is incremented by 1, thus generating an additional '+1' count sequence. An example is shown in Figure 10 for a divide ratio of 596+2/5. The values for M, A, B are calculated using the integer value (596) as in the previous example. The fractional denominator is programmed as 5 and the fractional numerator as 2. At the end of the first count cycle (596) the fractional counter is incremented to 2. At the end of the third count cycle the fractional N counter overflows, incrementing the A counter by 1 which gives a subsequent count cycle of 597. After five count cycles the sequence repeats with a total count of 2982 over the five count cycle giving a mean value of 596 + 2/5.
Total Count Cycle
Count Value
596
596
597
596
597
596
Fractional N Counter
0
2
4
1
3
0
2
Initial A Counter Value
4
4
5
4
5
4
Figure 10 - UHF Synthesizer - Fractional N Operation A result of this count sequence is that the output phase of the total counter changes through the count cycle, which causes the output pulse from the phase detector, and therefore the charge pump, to vary. This would cause large fractional spurs on the synthesizer output. These spurs can be compensated by applying a current pulse with the opposite polarity to the charge pump output. This compensation pulse has a fixed width of two reference clock (TCXO) periods; the amplitude is proportional to the value in the fractional N counter. The correction current is scaled by a 8 bit compensation DAC, with an externally provided input from the serial bus. This allows performance to be optimized in a given application. The compensation value can be calculated from the following formula: Comp Value = 255 - INT((Icp * Ftcxo)/(0.0245 * 6 * MOD *Fvco)) where Icp = charge pump current (uA)
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Zarlink Semiconductor Inc.
ZL20200
Ftcxo MOD Fvco = Reference frequency = Fractional Modulus = UHF VCO Frequency
Data Sheet
The synthesizer provides a lock detect output. When the output pulse from the phase detector is less than half a reference clock period an in-lock signal is generated. These in-lock signals then clock a 4 bit counter into which a threshold value has been programmed. When the required number of successive in-lock pulses have been generated the lock detect output is set. The ZL20200 has a single lock detect output pin for the UHF synthesizer and VHF synthesizers. The lock detect signal is asserted when all active synthesizers are in lock. If a synthesizer has not been enabled in the power control registers then that synthesizer will be inactive and will have no effect on the lock detect output.
1.5
VHF Frequency Synthesizers
The ZL20200 includes two VHF synthesizers to generate the second LO for the receiver and the transmit IF. They operate with their respective on-chip VHF VCO's and off-chip loop filters. The tank circuits and tuning components for the VCO's are also off chip. The two synthesizers are identical and are shown in Figure 11.
Lock Detect TCXO Reference Counter 14 bit Phase Detector VHF LO Dual Modulus Prescaler 16/17 +1 M Counter 13 bit Charge Pump
VHF CP
A 4 bit
Figure 11 - VHF Frequency Synthesizer The synthesizer uses a 2 modulus 16/17 prescaler with an 'M' counter and an 'A' swallow counter. This allows maximum flexibility when using this synthesizer. The reference counter is a simple 14 bit counter. All counter values are programmed via the serial bus and programming details are shown in the programming section. Both counters operate as count down. At the start of a count the counters are loaded with their respective values. The initial prescaler ratio is 17 assuming A > 0; when the A counter reaches zero the prescaler ratio is 16 until the M counter reaches zero. The complete process is then repeated. The total divide ratio (N) for this type of counter is given by N = 16*M + A M is always greater then A The values of M and A can be easily calculated from the total divide ratio N. M = INT (N/16) A = N - 16*M
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Zarlink Semiconductor Inc.
ZL20200
Data Sheet
The maximum value for A is 15 and M must always be greater than A. The VHF PLLs do not have fractional N capability however it is recommended that they are operated at as high a comparison frequency as allowed by the chosen frequency plan to minimize spurs levels. Both VHF synthesizers have lock detection circuits. These operate in the same way as described for the UHF synthesizer.
1.6
Internal Clock Generation
ZL20200 can use 14.4 MHz or 19.44 MHz reference frequency. The appropriate reference must be programmed via the serial bus. The clock signals for the switched capacitor filters and FM demodulator are generated from the reference TCXO signal. The internal divide ratios are switched to give the correct ratio.
From PLL Loop Filter 10k VCO+ 18p nm 43R
10k
18p
43R 33n
VCO-
Figure 12 - Typical VCO Tank Circuit
1.7
VHF VCO
ZL20200 has two VHF VCOs which operate with the VHF PLLs to provide the IF LO signals for both receive and transmit IF signals. The oscillators are a differential design and require an external tank circuit. A basic circuit with varactor is shown in Figure 12. It is recommended to include series resistors (e.g. 43 ohms) in each arm of the tank circuit to prevent any spurious high frequency oscillation due to parasitic capacitances.
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Zarlink Semiconductor Inc.
ZL20200
1.8 Power Supply Connections
Data Sheet
The circuit blocks within ZL20200 have separate supply connections to minimize interaction between circuit blocks. Details are shown in the earlier `Pin Names' section. These supplies are also grouped to allow different groups of supply pins to be connected to separate supplies for example, receive or transmit. These groups are shown below:
VCC - Control Supply Pin No. 56 Pin Name VCC CONTROL
VCC - TxRx Common (Synth) Pin No. 5 7 13 38 8 9 VCC - Rx Pin No. 49 50 VCC - Tx Pin No. 15 24 31 16 19 Pin Name VCC TX RF VCC TX VCC TX PLL TX 900 TX 1900 Pin Name VCC RX PLL VCC RX Pin Name VCC UHF PLL VCC UHF LO OUT VCC UHF LO VCC VHF CP 900 LO OUT 1900 LO OUT
Table 4 - Power Supply Connections The LO OUT and TX 900/1900 pins require bias and are normally connected to VCC through an inductor. All supply pins within a group must be powered together. Each group of pins can be powered up independent of the other groups.
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Zarlink Semiconductor Inc.
ZL20200
2.0 Programming and Control
Data Sheet
Programming via the serial bus is via 24 bit words with a 4 bit address as shown below
23 22 21 20 19 18 17 17 15 14 Data 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address
Bit23 (MSB) is loaded first. Bits 3:0 are used as address bits for the control registers. Details of serial bus timing are shown in Figure 13.
SCLK
t1
t2
t3 t6
SDAT
Bit 23
Bit 22
Bit 21
Bit 0
SLATCH
t4
t5
ENABLE1/2
t7
Figure 13 - Serial Bus Timing Enable1 and Enable2 need only be asserted after loading registers 0 to 3, the power control registers. These registers should be loaded with Enable1 and Enable2 low. All other registers can be loaded with Enable1 and Enable2 high or low.
2.1
Power Control Registers - Address 0 to 3
These registers are used in conjunction with the TX RXB and ENABLE1 and ENABLE2 control pins to power up the required sections of the device for any required mode. This enables power consumption to be optimized under all conditions. Figures 4 - 7, which show the receive and transmit paths in detail, show which sections are powered up by each control bit.
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Zarlink Semiconductor Inc.
ZL20200
The assignment is common for each of the registers 0 to 3 and is shown below. Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Not used Receive Baseband section UHF LO Buffer Receive VHF VCO UHF synthesizer Receive RSSI circuit Not used Receive Quadrature down-converter Receive VHF PLL Receive IF input Receive AGC amplifier Transmit reconstruction filters Transmit RF Transmit UHF LO UHF LO input buffer Transmit IF Transmit quadrature modulator Transmit VHF PLL Transmit VHF VCO Transmit up-converter IF input Table 5 - Power Control Registers
Note 1: Note 2:
Data Sheet
Circuit Section
If a bit is set to logic 1 then that circuit section is powered on. UHF LO input (bit 9) must be enabled for Transmit UHF LO (bit 10), UHF synthesizer (bit 19) and UHF LO Buffer (bit 21) to be active.
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Zarlink Semiconductor Inc.
ZL20200
The 4 registers address 0 to 3 are assigned as follows: Register Address 0 Register Name Receive
Data Sheet
Description All circuit blocks required in receive mode should be set to 1. This register will be selected when TX RXB is low. No circuits will be actually powered up if ENABLE1 and ENABLE 2 are both low. Transmit register All circuit blocks required in transmit mode should be set to 1. In duplex modes e.g. AMPS then both receive and transmit circuits must be selected. This register will be selected when TX RXB is high. No circuits will be actually powered up if ENABLE1 and ENABLE 2 are both low This register determines which circuit sections are powered up when ENABLE1 is high. The contents of this register are logical ANDed with the contents of the Receive or Transmit register as selected by TX RXB input. This register determines which circuit sections are powered up when ENABLE2 is high. The contents of this register are logical ANDed with the contents of the Receive or Transmit register as selected by TX RXB input. Table 6 - Power Control Register Functions
1
Transmit
2
ENABLE1 Configuration ENABLE2 Configuration
3
A feature of this programming approach is that once a phone operating mode has been selected and set up via the serial bus, all power control can then be via the TX RXB, ENABLE1 and ENABLE2 control pins. Alternatively full power control is possible via the 3 wire serial bus without the use of any external control pins. If ENABLE1 and ENABLE2 are both low then the device is in Sleep mode. No circuits will be enabled unless either ENABLE1 or ENABLE2 are high regardless of the contents of the receive and transmit registers. An example of how these control bits can be used, is that the oscillators and PLL circuits can be powered up and allowed to settle prior to powering up the complete transmit or receive path. In the case of the receive path the UHF synthesizer, UHF LO input buffer, UHF LO Buffer and Receive VHF VCO, Receive VHF PLL bits would be set in the ENABLE1 Configuration register. The ENABLE2 Configuration register would contain these bits plus the remainder of the receive path bits, Receive IF input, Receive AGC amplifier, Receive quadrature down-converter and receive baseband section. This is demonstrated in the following examples.
2.1.1
Power Control Modes - TDMA (IS136)
In a TDMA system the transceiver will either operate in receive only, or transmit only mode. It is assumed that an interim power on state will be used during which the oscillators and PLLs will be set up, and allowed to settle prior to activating the full signal path. The suggested programming for the power control registers (0 - 3) is shown in the table below. Enable 1 Config. Addr 2 0 0 Enable 2 Config. Addr 3 0 1
Bit 23 22 Not used
Circuit Section
Receive Addr 0 0 1
Transmit Addr 1 0 0
Comments
Receive Baseband section
Table 7 - Programming for the Power Control Registers (0 - 3)
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Zarlink Semiconductor Inc.
ZL20200
Circuit Section UHF LO Buffer Receive VHF VCO UHF synthesizer Receive RSSI circuit Not used Receive Quadrature down-converter Receive VHF PLL Receive IF input Receive AGC amplifier Transmit reconstruction filters Transmit RF Transmit UHF LO UHF LO input buffer Transmit IF Transmit quadrature modulator Transmit VHF PLL Transmit VHF VCO Transmit up-converter IF input Receive Addr 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 Transmit Addr 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Enable 1 Config. Addr 2 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 Enable 2 Config. Addr 3 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Data Sheet
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
Comments Note 1
Note 2
Table 7 - Programming for the Power Control Registers (0 - 3) (continued)
Note 1: Note 2: Not required if driving external receive mixer direct from UHF VCO. Can be used for IS136 if required.
The receive register contains all bits required when in receive mode: the transmit register contains all bits required in transmit mode. The Enable1 configuration register contains all bits required to power up oscillators and synthesizers in both receive and transmit mode. The Enable2 configuration register contains all bits required to power up the complete receive and transmit modes (this register can be set to all '1's if preferred). The following words should therefore be programmed on the serial bus (Hex format): Receive register (0) Transmit register (1) Enable1 Config. register (2) Enable2 Config. register (3) 59E200 081FF1 188262 59FFF3
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Zarlink Semiconductor Inc.
ZL20200
2.1.2 Power Control Modes - AMPS
Data Sheet
When operating in AMPS mode the ZL20200 will operate in either Receive only or Duplex. The enable registers should therefore be programmed as shown below.
Enable 1 Config. Addr 2 Enable 2 Config. Addr 3
Bit
Circuit Section
Receive Addr 0
Transmit Addr 1
Comments
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
Not used Receive Baseband section UHF LO Buffer Receive VHF VCO UHF synthesizer Receive RSSI circuit Not used Receive Quadrature downconverter Receive VHF PLL Receive IF input Receive AGC amplifier Transmit reconstruction filters Transmit RF Transmit UHF LO UHF LO input buffer Transmit IF Transmit quadrature modulator Transmit VHF PLL Transmit VHF VCO Transmit up-converter IF input
0 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 0 0
0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0
0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1
Table 8 - Enable Registers
Note 1: Not required if driving external receive mixer direct from UHF VCO.
The receive register contains all bits required when in receive mode: the transmit register contains all bits required in duplex mode. The Enable1 configuration register contains all bits required to power up oscillators and synthesizers in both receive and duplex mode. The Enable2 configuration register contains all bits required to power up the complete receive and duplex modes (this register can be set to all '1's if preferred). The following words should therefore be programmed on the serial bus (Hex format): Receive register (0) Transmit register (1) 5DE200 5DFFF1
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Zarlink Semiconductor Inc.
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Enable1 Config. register (2) Enable2 Config. register (3) 188262 5DFFF3
Data Sheet
2.2
Operating Register Address 4
This registers selects internal setups for example IS136. The bits are assigned for control of receive and transmit bits as shown below:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 2 1 1 0 0 0
RX<7:0> Receive Set Up
TX <11:0> Transmit Set Up
Address
The function of the receive bits is shown below: Register Bit No. 23 22 21 20 19 18 17 16 Control Bit RX<7> RX<6> RX<5> RX<4> RX<3> RX<2> RX<1> RX<0> LO output = 900 MHz Receive output dc bias (I/Q) = 1.25 V IS136 Mode IF1 Input enabled AMPS IF Input 0 selected
Action if '0' Receive DLL disabled Bandpass Filter BW = +/- 20 kHz
Action if '1' Receive DLL enabled Bandpass Filter BW = +/- 16 kHz Not Used. Set to `0'. LO Output = 1900 MHz Receive output dc bias (I/Q) = Vcc/2 Not Used IS136 IF Input 1 selected
Table 9 - Function of the Receive Bits Bit 23 RX<7> is only applicable when VCO divide by 2 mode is selected in register 5
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Zarlink Semiconductor Inc.
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The function of the transmit bits is shown below: Register Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 Control Bit TX<11> TX<10> TX<9> TX<8> TX<7> TX<6> TX<5> TX<4> TX<3> TX<2> TX<1> TX<0> 900 MHz output Internal IS136 baseband filters Transmit baseband filters selected 1900 MHz output External transmit IF Filter Not Used
Data Sheet
Action if '0'
Action if '1'
Transmit output stage gain control
Control of RF Transmit output stage current with VGA control voltage. Nominal value for TX<11:4> is 101010
Transmit baseband filters by-passed
Table 10 - Function of the Transmit Bits Control bits TX<11:4> allow optimization of the transmit output stage. This allows variation of the decrease in supply current with decreasing agc voltage and also allows optimization depending on output power and linearity requirements. Figure 14 shows the variation of output stage supply current with agc voltage and the programmable characteristics. The maximum current, agc threshold and slope can be programmed. The minimum current is not programmable. TX<11:10> (bits 15,14) allow the gain of the transmit output stage to be varied in 3 dB steps as shown in the table below: TX<11> 0 0 1 1 TX<10> 0 1 0 1 Gain (dB) -6 -3 Nominal +3
Table 11 - Gain of the Transmit Output Stage
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Zarlink Semiconductor Inc.
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Data Sheet
Imax Icc Imin Slope
Vagc
Vth
Figure 14 - Transmit Output Stage Current versus Gain Control TX<9:8> (bits 13:12) control the agc voltage (Vth) at which the output stage current starts reducing. Typical values are shown in the table below: TX<9> 0 0 1 1 TX<8> 0 1 0 1 Vth (V) 1.09 1.25 1.48 1.81
Table 12 - VGA Threshold Voltage TX<7:6> (bits 11,10) control the rate of current reduction as shown in Figure 14. Typical vales are shown in the below: TX<7> 0 0 1 1 TX<6> 0 1 0 1 Slope (mA/V) 65 75 90 105
Table 13 - VGA Current Reduction TX<5:4> (bits 9:8) adjust the maximum current (Imax) of the transmit output stage. The gain of the output stage is not changed. Typical values are shown in the table below: TX<5> 0 0 1 1 TX<4> 0 1 0 1 Current 25% 50% Nominal 150%
Table 14 - Output Stage Current
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Data Sheet
Using these controls allows the performance of the output stage to be optimized under various conditions; for example, current cant can be reduced if non-linear operation is required. The nominal value recommended for TX<11:4> is 10101010. An example of setting up the control register (address 4) for various systems is shown below:
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Name RX<7> RX<6> RX<5> RX<4> RX<3> RX<2> RX<1> RX<0> TX<11> TX<10> TX<9> TX<8> TX<7> TX<6> TX<5> TX<4> TX<3> TX<2> TX<1> TX<0> IS136 - (900) 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 IS136 - (1900) 0 0 0 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 0 AMPS 0 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 Note 2 Note 1 Comments
Table 15 - Control Register Settings
Note 1: Note 2: The setting for RX<3> is dependent on the optimum common mode input voltage of the analog to digital converter in the baseband. Selects external transmit IF filter if used.
The following hex words are therefore recommended for the control register (address 4): IS136 (900) IS136 (1900) AMPS 03AA04 13AAC4 41AA04
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2.3 Synthesizer Register - Address 5
Data Sheet
This register sets up LO options for receive and transmit and also UHF synthesizer set up.
23 22 21 20 19 18 17 16 0 UI RX LO2 Set Up UC DL UD TX LO Set Up UHF PLL Set Up 15 14 13 12 11 10 9 8 7 6 5 4 3 0 2 1 1 0 0 1
Address
Bits 23,17,14 are also used for UHF PLL and LO set up. Bits 16,15 are not used and should be set to zero.
2.3.1
UHF PLL and LO
Action if '0' UHF PLL input = 900 MHz Action if '1' UHF PLL input = 1900 MHz Fractional N Compensation selected UHF Doubler Selected Fractional N Denominator - see table below
Register Bit No. 23 17 14 8 7 6 5 4
Not Used - Set to 0 UHF PLL Charge Pump Current - see table below
Table 16 - UHF PLL and LO Control
Note 1: Note 2: Note 3: Note 4: Bit 14 is only effective if 1900 MHz mode has been selected (register 4 Bit 7). Bit 23 is only effective if 1900 MHz mode has been selected (register 4 Bit 7) and the UHF frequency doubler selected (Register 5 Bit 14). This control allows the use of the doubled frequency to be used as the input to the UHF PLL. Fractional N Denominator. Bits 8,7 select the fractional N denominator for the UHF PLL as shown below:
<8> 0 0 1 1
<7> 0 1 0 1
Frac N Denom. 5 8 13 20
Table 17 - Fractional N Denominator
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Zarlink Semiconductor Inc.
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2.3.2 UHF PLL Charge Pump Current
Data Sheet
Bits 5,4 select the charge pump current for the UHF PLL as shown below: <5> 0 0 1 1 <4> 0 1 0 1 Current (mA) 1.00 0.50 0.25 0.125
Table 18 - UHF PLL Charge Pump Current
2.3.3
Receive LO Set Up
Action if '0' High side Rx second LO injection Rx second LO = VCO/2 Rx LO phase detector polarity normal Action if '1' Low side Rx second LO injection Rx second LO = VCO/4 Rx LO phase detector polarity inverted
Register Bit No. 22 21 20 19 18
Receive VHF PLL Charge Pump Current - see table below
Table 19 - Receive LO Set Up Bits 19,18 select the charge pump current for the receive VHF PLL as shown below: <19> 0 0 1 1 <18> 0 1 0 1 Current (mA) 1.00 0.50 0.25 0.125
Table 20 - Receive VHF PLL Charge Pump Current
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2.3.4 Transmit LO Set Up
Register Bit No. 15 13 12 11 10 9
Data Sheet
Action if '0' Transmit DLL disabled Low side Tx up-converter LO injection Tx second LO = VCO/2 Tx LO phase detector polarity normal
Action if '1' Transmit DLL enabled High side Tx up-converter LO injection Tx second LO = VCO/4 Tx LO phase detector polarity inverted
Transmit VHF PLL Charge Pump Current - see table below Table 21 - Transmit LO Set Up
Bits 10,9 select the charge pump current for the receive VHF PLL as shown below: <10> 0 0 1 1 <9> 0 1 0 1 Current (mA) 1.00 0.50 0.25 0.125
Table 22 - Transmit VHF PLL Charge Pump Current
2.4
23 0
Control Register - Address 6
22 21 20 19 18 0 BBG TCXO PDF LPC Tx Gain R Mode Control 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 2 1 1 1 0 0
Address
2.4.1
IS136 Baseband Gain
Bits 22:21 can be used to vary the gain of the baseband output stages in IS136 mode only. The gain of the 60 kHz IF stage preceding the baseband mixer is also varied so that the overall gain of the device can be maintained if required. The nominal gain is 20 dB and the recommended setting is BBG<1:0> = 11 to minimize output dc offsets. BBG<1> Bit 22 0 0 1 1 BBG<0> Bit 21 0 1 0 1 IF Gain (dB) 14 17 17 20 Table 23 - Baseband Gain Baseband Gain (dB) 6 6 0 0 Overall Gain (dB) 20 23 17 20
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2.4.2 TCXO Reference Selection
Data Sheet
Bits 20:19 are used to set the device to the required TCXO reference frequency. TCXO<1> Bit 20 0 1 TCXO<0> Bit 19 1 0 TCXO Frequency (MHz) 14.4 19.44
Table 24 - TCXO Reference Selection
2.4.3
Discriminator Output Filtering
Bits 17:14 set up on chip filtering of the FM output signal and are therefore only used in AMPS mode. Two cascaded filters can be selected and the bandwidth can be set to 25 or 37.5 kHz cut-off. Bits 17,16 (PDF) select the filters and bits 15,14 set the cutoff frequency. <17> 0 0 1 1 X X X X <16> 0 1 0 1 X X X X <15> X X X X 0 0 1 1 <14> X X X X 0 1 0 1 No filters Filter 1 selected Filter 2 selected Filters 1 and 2 selected Both filters 37.5 kHz Filter 1 25 kHz, Filter 2 37.5 kHz Filter 1 37.5 kHz, Filter 2 25 kHz Both filters 25 kHz Filter Selection
Table 25 - FM Discriminator Output Filter Control In IS136 mode Bits <17:14> should be set to 0000. It is recommended that if the additional discriminator filtering is required in AMPS mode then both filters should be used with 25 kHz bandwidth, i.e. Bits<17:14> should be set 1111.
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2.4.4 Transmit Baseband Gain
Data Sheet
Bits 13:11 set the transmit baseband gain as shown below: <13> 0 0 0 0 1 <12> 0 0 1 1 0 <11> 0 1 0 1 0 Gain 0 3 6 9 12 (dB)
Table 26 - Transmit Baseband Gain
2.4.5
Mode Control
Bit 10 resets the contents of all registers to '0'. After the reset is complete bit 10 is also reset to '0'. Bits 9:4 allow TXRXB, ENABLE1 and ENABLE2 to be programmed by either the external pins or via the serial bus. This allows mode control to be either via the external pins or the serial bus. The default state is using the external pins as this allows more accurate timing of power control. Register Bit No. 9 8 7 6 5 4 TXRXB Pin (34) selected Enable2 Pin (20) selected Enable1 Pin (11) selected Action if '0' Receive Register (0) selected Action if '1' Transmit Register (1) selected Enable2 Configuration Register (3) selected Enable1 Configuration Register (2) selected Serial Bus selected - Bit 9 Serial Bus selected - Bit 8 Serial Bus selected - Bit 7
Table 27 - Mode Control Bits 9:7 can only be used if the appropriate bits 6:4 have been set to disable the external pins. If serial mode has been selected then the operation of bits 9:7 is the same as the external TX RXB, ENABLE1 and ENABLE2 pins respectively.
2.5 2.6
Register Address 7 - Not Used Test Mode Register - Address 8
This register is used for test purposes only and should not be used.
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2.7
23
Data Sheet
UHF PLL Divider Programming Register - Address 9
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 M Counter Value B Counter Value A Counter Value 2 0 1 0 0 1
Address
Bits 23:11 set M counter value (Bit 23 = MSB) Bits 10:8 set B counter value - max value = 7 (Bit 10 = MSB) Bits 8:4 set A counter value - max value = 8 (Bit 7 = MSB) The A counter is a 4 bit counter to enable correct fractional N operation. Valid values of A are in the range 1 to 8. Using the 64/65/72/73 four modulus prescaler the divide ratio (N) is given by: N = 64 * M + 8 * B + A Values of M, B, A can be easily calculated using the formulae in the synthesizer section.
2.8
23 0 X
UHF PLL Reference Divider and Fractional N Programming Register - Address 10
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 Frac N Numerator UHF PLL Reference Counter Value 2 0 1 1 0 0
Address
Bit 23 is unused and should be set to '0' Bits 22:18 set the fractional N numerator (Bit 22 = MSB) Bits 17:4 set the Reference counter value (Bit 17 = MSB)
2.9
23 0 X
Receive VHF PLL Divider Programming Register - Address 11
22 0 X 21 0 X M Counter Value A Counter Value 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 2 0 1 1 0 1
Address
Bits 20:8 set M counter value (Bit 20 = MSB) Bits 7:4 set A counter value - max value = 15 (Bit 7 = MSB) Using the 16/17 two modulus prescaler the divide value (N) is given by: N = 16 * M + A Values of M, A can be easily calculated using the formulae in the synthesizer section.
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2.10
23 0 X
Data Sheet
Receive VHF PLL Reference Divider Programming Register - Address 12
22 0 X 21 0 X 20 0 X 19 0 X RS Receive VHF PLL Reference Counter Value 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 2 1 1 0 0 0
Address
Bits 23:19 are unused and should be set to '0' Bit 18 selects common reference divider for VHF receive and transmit PLLs ('0' to select). If a common reference divider is selected then the transmit VHF reference divider is used which must be programmed in register 13. Bits 17:4 set the Reference divider value (Bit 17 = MSB)
2.11
23 0 X
Transmit VHF PLL Divider Programming Register - Address 13
22 0 X 21 0 X M Counter Value A Counter Value 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 2 1 1 0 0 1
Address
Bits 23:21 are unused and should be set to '0' Bits 20:8 set M counter value (Bit 20 = MSB) Bits 7:4 set A counter value - max value = 15 (Bit 7 = MSB) Programming is identical to that for the receive VHF PLL register 11.
2.12
23 0 X
Transmit VHF PLL Reference Divider Programming Register Address 14
22 0 X 21 0 X 20 0 X 19 0 X 18 0 X Transmit VHF PLL Reference Counter Value 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 2 1 1 1 0 0
Address
Bits 23:18 are unused and should be set to '0' Bits 17:4 set the Reference counter value (Bit 17 = MSB)
2.13
23
PLL Lock Detect & Fractional N Compensation Programming Register Address 15
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 Fractional N Compensation UHF PLL Lock Count Transmit VHF PLL Lock Count Receive VHF PLL Lock Count 2 1 1 1 0 1
Address
2.13.1
Fractional N Compensation
Bits 23:16 set the value for fractional N compensation in the UHF PLL with bit 23 as MSB. The value for the compensation is dependent on a number of parameters which are described in the synthesizer section.
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2.13.2 PLL Lock detect counters
Data Sheet
These 4 bit counters count the consecutive comparison cycles where the lock detect circuit gives an in-lock result. When the counter reaches its programmed count then that PLL is deemed to have achieved full lock. This prevents spurious false in-lock signals while the PLL is achieving lock up. There are separate counters for the UHF, Rx VHF and Tx VHF PLLs which are programmed as shown above. Bits 15,11,7 are the MSB's for the UHF, Rx VHF and Tx VHF PLL lock detector counters respectively. A non zero value must be programmed for the lock detect to operate correctly.
3.0
Absolute Maximum Ratings
-0.3 to 3.6 V -0.3 to Vcc + 0.3 V -40C to 85C -55C to 125C 125C
Supply Voltage Voltage applied to any pin Operating Temperature Storage Temperature Max Junction Temperature
This device is sensitive to ESD. Most pins have an ESD rating greater than 2000 V (Human Body Model HBM), however some pins have limited protection (800 to 2000 V) in order to meet the RF performance requirements. Anti-static precautions should be used when handling this device.
4.0
Operating Conditions
Device operation is guaranteed under the following conditions: Operating Conditions Condition
General Supply Voltage Operating Temperature 2.7 -40 3.3 +85 V C
Min.
Value Type
Max.
Units
Comments
Logic Input Voltage High - VIH Logic Input Voltage Low - VIL
0.8Vcc 0.2Vcc
Volts Volts
TCXO Reference Frequency Frequency Frequency 14.4 19.44 MHz MHz
Receiver Receiver IF Frequency 70 215 MHz
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Operating Conditions (continued) Condition
Transmitter Transmit IF Frequency I & Q common mode voltage I & Q input voltage level 50 1.2 1.5 215 MHz V V p-p
Data Sheet
Min.
Value Type
Max.
Units
Comments
0dB input buffer gain
Cellular band LO input level PCS band LO input level Cellular band LO frequency PCS1900 band frequency
-15 -15 900 1900
-10 -10
-5 -5 1100 2200
dBm dBm
MHz
Serial Control Timing SDATA Set Up t1 SDATA Hold t2 SCLK Pulse Width t3 SLATCH Set up t4 SLATCH Pulse Width t5 SCLK Period t6 Power Control Set up t7 20 20 50 20 50 100 20 ns ns ns ns ns ns ns
See Figure 13
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5.0 Electrical Characteristics
Data Sheet
The electrical characteristics are guaranteed under the following conditions unless stated otherwise. Vcc =3.0 V, T = 25C, TCXO Ref Frequency = 19.44 MHz.
Value Typ
Characteristics Supply Current Sleep
Min.
Max.
Units
Comments
10
40
A
Logic inputs = 0 V or Vcc
Receive Operation AMPS IS136 32 33 38 39 mA mA Note 1, AGC = 1.6 V Note 1, AGC = 1.6 V
Transmit Operation 900 MHz Output 141 106 170 125 mA mA VGA = 2.4 V, Note 2 VGA = 1 V, Note 2
1900 MHz Output
120 102
145 120
mA mA
VGA = 2.4 V, Note 2 VGA = 1 V, Note 2
Standby Operation UHF PLL Receive VHF PLL Transmit VHF PLL 12.5 5.2 4.9 15.0 6.3 6.0 mA mA mA Note 3
Additional Circuits Frequency Doubler UHF LO Output Buffer Logic Inputs Input Current Input Capacitance Lock Detect Output Output Voltage Low Output Voltage High TCXO Input 0.8Vcc 0.2Vcc Volts Volts I out = 1 mA I out = -1 mA 10 10 nA pF Vin = 0 to Vcc 4 4.5 5 5.5 mA mA Note 4 900 or 1900 Band Note 5
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Characteristics Input Resistance Input Capacitance Input Sensitivity 0.5 Min. 10 10 2 Value Typ Max. Units k pF V p-p ac coupled Comments
Data Sheet
Receiver - IS136
All parameters are measured at an IF frequency of 135.06 MHz, Rx VCO = 270 MHz unless stated otherwise 500 80 91 -13 50 56 8 101 104 74 +/- 0.5 +/- 2 3 +/-20 5 62 1500 W dB dB dB/V dB dBV dBV dB V p-p mV AGC = 2.4 V AGC = 0.3 V AGC = 0.3 to 2 V Rs =800 Minimum gain Max Gain
Input impedance Max Voltage Gain Min Voltage Gain Gain slope NF Gainmax Input V1dB Gainmin IIP3 Gainmax I/Q Amplitude Matching I/Q Quadrature Accuracy Output 1 dB Compression Output dc Offset
Receiver AMPS (Fixed Gain)
All parameters are measured at an IF frequency of 135.06 MHz, Rx VCO = 270 MHz unless stated otherwise. Vagc = 1.6 V (Gain 20 dB below maximum) 500 14 12 93 900 1000 50 -3 16 25 75 0.35 0.5 0.70 +3 1100 1500 W dBV dB dBV mV dB dB mV/dB dBV dBV Note 7 Note 6
Input impedance Input Sensitivity Noise Figure Input IP3 Audio Output RSSI Dynamic Range Accuracy RSSI Slope Input Signal - Min Input Signal - Max Min RSSI Level
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Characteristics Max RSSI Level RSSI Output Impedance Min. 1.45 Value Typ 1.55 1 Max. 1.65 Units V k Comments
Data Sheet
Bandpass Filter IS136 and AMPS Centre Frequency 3 dB Bandwidth +/- 16 60 +/- 18 kHz kHz
Narrow bandwidth mode
Stop Band Attenuation 0 to 3 kHz 3 kHz to 10 kHz 10 kHz to 22 kHz 38 kHz 82 kHz 98 kHz to 110 kHz 110 kHz to 117 kHz 117 kHz to 123 kHz 123 kHz to 1.36 MHz 1.36 MHz to 1.52 MHz 1.52 MHz to 10 MHz Image Attenuation 0 to -10 kHz -10 kHz to -42 kHz - 42 kHz to -78 kHz - 78 kHz to -105 kHz -105 kHz to -1.36 MHz -1.36 MHz to -1.52 MHz -1.52 MHz to -10 MHz 61 40 30 40 61 36 61 48 40 dB dB dB dB dB dB dB 67 61 48 18 18 48 61 68 71 36 71 69 63 51 20 20 50 63 70 73 48 73 dB dB dB dB dB dB dB dB dB dB dB
Relative to signal at 60 kHz
Gain Ripple
1.0
1.5
dB
60 kHz +/- 12.5 kHz
Transmitter
All parameters are measured at an IF frequency of 180.0 MHz, Tx VCO = 360 MHz unless stated otherwise
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Characteristics I & Q modulator I/Q Input Buffer Gain I/Q Input Buffer Gain I/Q Input Buffer Gain I/Q Input Buffer Gain I/Q Input Buffer Gain I & Q differential input resistance I & Q Baseband Filter Attenuation (IS136/AMPS) dc - 12.5 kHz 85 - 180 kHz > 180 kHz 12 25 17 33 0.5 dB dB dB 80 -1 0 3 6 9 12 +1 dB dB dB dB dB k Min. Value Typ Max. Units Comments
Data Sheet
Carrier Suppression Sideband Suppression
30 30
40 40
dB dB
IF Variable gain amplifiers Gain control range Control voltage for minimum gain Control voltage for maximum gain AGC control voltage slope 33 38 45 0.10 2.4 43 60 dB V V dB/V VGA = 0.5 to 1.2 V
IF Output Filter (option) IF output impedance IF input impedance IF output level 500 1.5 100 W k mV To external filter From external filter
800 MHz RF output stage
Specifications assume 50 ohm load driven via a matching network. Output Frequency = 836 MHz, UHF LO = -10 dBm at 1016 MHz. 824 +8 +10 849 MHz dBm
RF amplifier operating frequency range Output power
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Characteristics ACPR (TDMA) Min. Value Typ -36 -56 Output power AMPS Receive band noise (869 - 894 MHz) Spurious Outputs LO Leakage Image Rejection Other Spurii -25 -27 -21 -21 -20 dBc dBc dBm Pout = +8 dBm Pout = +8 dBm +10 +14 -124 Max. Units dBc dBc dBm dBm/Hz Comments
Data Sheet
Pout = +8 dBm, Offset = 30 kHz Pout = +8 dBm, Offset = 60 kHz
ftx = 849 MHz Pout = +8 dBm With external IF filter
1900 MHz RF output stage (PCS)
Specifications assume 50 ohm load driven via a matching network Output Frequency = 1880 MHz, UHF LO = -10 dBm at 2060 MHz. 1.88 +8 +10 -36 -56 1.91 GHz dBm dBc dBc dBm/Hz Pout = +8 dBm, Offset = 30 kHz Pout = +8 dBm, Offset = 60 kHz ftx = 1910 MHz, Pout = +8 dBm With external IF filter
RF amplifier operating frequency range Output power ACPR (TDMA)
Receive band noise (1930-1990 MHz) Spurious Outputs LO Leakage Image Rejection Other Spurii
-128
-30 -30
-25 -25 -20
dBc dBc dBm
Pout = +8 dBm Pout = +8 dBm
UHF Synthesizer Input Frequency Charge Pump Current 800 0.9 0.45 0.22 0.11 Charge Pump Output Compliance Charge Pump sink/source mismatch 0.4 1 0.5 0.25 0.125 2200 1.1 0.55 0.28 0.14 Vdd - 0.4 15 MHz mA mA mA mA V % Less than +/-10% variation in Iout
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Characteristics Charge Pump off-state current Fractional Compensation 88 Min. Value Typ 5 98 108 Max. Units nA A Full Scale Comments
Data Sheet
UHF Buffers Load Impedance Output Level (900 and 1900) Harmonic Level 200 -11 -40 W dBm dBc Load = 200 ohms LO1900 Output
Rx and Tx IF Synthesizers Input Frequency Charge Pump Current 100 0.9 0.45 0.22 0.11 Charge Pump Output Compliance Charge Pump sink/source mismatch Charge Pump off-state current 5 0.4 1 0.5 0.25 0.125 430 1.1 0.55 0.28 0.14 Vcc - 0.4 15 MHz mA mA mA mA V % nA Less than +/-10% variation in Iout
Rx LO Oscillator Frequency Phase Noise 140 -99 430 MHz dBc/Hz Freq = 270 MHz, Offset = 30 kHz
Tx LO Oscillator Frequency Phase Noise
Notes: Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: All receive currents include all receiver sections plus Rx VHF and UHF PLL's, and UHF LO input buffer circuits. The LO output buffer and frequency doubler are not included. All transmit currents include all transmit sections plus Tx VHF and UHF PLL's, and UHF LO input buffer circuits. The LO output buffer and frequency doubler are not included. Includes UHF LO input buffer. This is only applicable in 1900 MHz band. The UHF LO output buffer need only be powered up if required to drive an external circuit, for example, a receive front end mixer. Input signal FM modulated with 8 kHz deviation by 1 kHz modulating signal. Specification is minimum input level to obtain 12 dB SINAD at FM Output (pin 45) using CCITT filter. Input modulation: 1 kHz modulating signal with 8 kHz deviation. Output level at FM out (pin 45) is set by external components. See application section for details.
260 -99
430
MHz dBc/Hz Freq = 360 MHz, Offset = 30 kHz
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Zarlink Semiconductor Inc.
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6.0
6.1
Data Sheet
Typical Performance Curves
Receive
IS136 Rx. - Icc v T emperature 35 34 33 32 mA 31 30 29 28 27 -40 25 T emperature C 85 Vcc = 2.7V Vcc = 3.0V Vcc = 3.3V
AMPS Rx. - Icc v Temperature
38 37 36 35 mA 34 33 32 31 30 29 -40 25 Temperature C 85
Vcc = 2.7V Vcc = 3.0V Vcc = 3.3V
Rx. Gain v AGC (Vcc) 120 100 80 dB dB 60 40 20 0 -20 0 1 AGC Volts 2 3 Vcc = 2.7V Vcc = 3.0V Vcc = 3.3V 120 100 80 60 40 20 0 -20 0
Rx. Gain v AGC (Temperature)
T = -40C T = 25C T = 85C
1 AGC Volts
2
3
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Zarlink Semiconductor Inc.
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Rx. RSSI 1.6 1.4 1.2 RSSI Voltage 1 0.8 0.6 0.4 0.2 0 -150 -100 -50 0 Input Level dBm
-40C 25C 85C
Data Sheet
6.2
Transmit
IS 3 T . 9 0M z- Ic vA C(V c 16 x 0 H cG c) 10 8 10 6 10 4 10 2
IS 3 T . 9 0M z - Ic vA C(T m e tu ) 16 x 0 H cG e p ra re 10 8 10 6 10 4 10 2 Ic m cA 10 0 8 0 6 0 4 0 2 0 -4 0C 2 5C 8 5C 0 1 A CV lts Go 2 3
Ic m cA
10 0 8 0 6 0 4 0 2 0 0 0 1 A CV lts Go 2 3 V c =2 V c .7 V c =3 V c .0 V c =3 V c .3
0
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Zarlink Semiconductor Inc.
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Data Sheet
IS 3 T . 1 0 M z- Ic vA C(V c 16 x 90 H c G c) 10 6 10 4 10 2 Ic m cA Ic m cA 10 0 8 0 6 0 4 0 2 0 0 0 1 A CV lts Go 2 3 V c=2 V c .7 V c=3 V c .0 V c=3 V c .3
IS 3 T .1 0 M z- Ic vA C(T m e tu ) 16 x 90 H cG e p ra re 10 6 10 4 10 2 10 0 8 0 6 0 4 0 2 0 0 0 1 A CV lts Go 2 3 -4 0C 2 5C 8 5C
IS 3 T . 9 0M z- P wr O t vA C( c ) 1 6 x 0 H o e u G Vc 2 0 1 0 0 -1 0 dm B dm B -2 0 -3 0 -4 0 -5 0 -6 0 0 1 A CV lts Go 2 3 V c=2 V c .7 V c=3 V c .0 V c=3 V c .3
IS 3 T . 9 0M z- P w r O t vA C(T m .) 16 x 0 H oe u G ep 2 0 1 0 0 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 0 1 A CV lts Go 2 3 -4 0C 2 5C 8 5C
48
Zarlink Semiconductor Inc.
ZL20200
IS 3 T . 1 0 M z- P w r O t vA C(V c 16 x 90 H oe u G c)
2 0
Data Sheet
IS 3 T 1 0 M z- P w r O t vA C(T m .) 16 x 90 H oe u G ep 2 0 1 0 0 -1 0 dm B -2 0 -3 0 -4 0 -5 0 -6 0 -4 0C 2 5C 8 5C
1 0
0
-1 0
dm B
-2 0
-3 0
V c=2 V c .7 V c=3 V c .0 V c=3 V c .3
-4 0
-5 0
-6 0
0
1 A CV lts Go
2
3
0
1 A CV lts Go
2
3
49
Zarlink Semiconductor Inc.
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